1. Field of the Invention
The present invention relates generally to the field of semiconductor processing, and more particularly, to a trench isolation process.
2. Description of the Related Art
As the demand for cheaper, faster, lower power consuming microprocessors increases, so must the device packing density of the integrated circuit (IC). All aspects of the IC must be scaled down to fully minimize the dimensions of the circuit. In addition to minimizing transistor dimensions, one must minimize the dimensions of the field regions (or isolation regions) which serve to physically and electrically isolate one semiconductor device from an adjacent semiconductor device on a semiconductor substrate, so that each device can operate independently of the other.
In general, the number of transistors that can be built on a silicon substrate is limited only by the size of the transistors and available surface area on the substrate. Transistors can only be built in active regions of a silicon substrate, with isolation regions of the substrate dedicated to separating active regions from one another. Therefore, to maximize the number of transistors on the surface of a silicon substrate, it is necessary to maximize the available active surface area of the substrate. The active surface area is maximized by, in turn, minimizing the isolation regions of the silicon substrate. In order to fully minimize an isolation region, the width of the isolation region should approach the minimum width printable by a given photolithographic technology.
One technology developed to form such isolation regions is known as trench technology. A trench isolation structure is formed in a silicon substrate by etching a trench region into the substrate and subsequently refilling the trench with some type of trench fill material. Thereafter, active regions adjacent to the trench isolation structure are available for conventional semiconductor processing to form transistors on the semiconductor device. For example, FIG. 1 provides a cross-sectional view of a semiconductor substrate 110 with a trench isolation structure formed therein. A trench sidewall oxide 160 lines the sidewalls of the trench, with the trench then filled in with an oxide to form the trench fill oxide 170. When forming a transistor adjacent to the trench, a gate insulating oxide layer 180 is grown over the substrate and over the trench.
There are several problems, however, that result from use of the trench isolation technology described briefly above. One such problem is the formation of the "bird's beak" or sharp top corners 190 of the trench. Sharp top corners 190 of the trench may carry stronger electric fields (e-fields) and cause problems later when forming active regions on either side of the trench. Because the top corners 190 of the trench are sharp, the thickness of the gate oxide layer 180 around the top corners 190 becomes very thin and the gate oxide layer 180 cannot be grown with uniform thickness. A thin gate oxide layer may break down if subjected to high electric fields. For example, once a transistor is formed and is functioning, the sharp top corners 190 create a high e-field and the thin gate oxide layer 180 may be subject to failure causing undesirable parasitic capacitances and leakage voltages that degrade device performances. As a result, the isolation technique described above is limited to fabricating devices that use a thin gate oxide layer of greater than 32 .ANG..
Sharp top corners can also cause a problem when filling the trench. As stated above, the trench is generally filled using chemical vapor deposition (CVD) techniques to fill the trench with materials such as an oxide, polysilicon, or a combination thereof. CVD processes subject the structure to plasma which also induces (or creates) an electric field around the sharp corners causing a non-uniform deposition process and may create gaps or voids in the trench fill.
Another problem resulting from trench isolation technology is the outdiffusion of dopants from the semiconductor device region, for example from the source 220 and drain 230 regions of a transistor (see FIG. 2), into the trench 245 region. Outdiffusion is especially prominent in N-channel transistors that have narrow widths. (Note that P-channel transistors may also have narrow widths, but N-channel transistors are more susceptible to outdiffusion because of boron well.) Thus, as device dimensions decrease (i.e., develop narrower widths) the susceptibility to outdiffusion increases. Outdiffusion of the dopants from the device region has several effects. It is well known in the art that the higher the dopant concentration the higher the threshold voltage of the transistor. Thus, dopant outdiffusion from the device region into the channel reduces the dopant concentration of the transistor and thus decreases the threshold voltage of the device. For example, if dopants in region 250 adjacent source region 220 outdiffuse into trench 245, then the dopant concentration in region 250 will be less than the dopant concentration in region 255. Therefore, the threshold voltage in region 250 will be less than the threshold voltage in the region 255.
The outdiffusion of dopants may also increase the off-leakage current. The off-leakage current is the parasitic (i.e., bad or unwanted) current that flows from the source 220 to the drain 230 of the transistor when the voltage applied to the gate 240 is zero (V.sub.g =0), and the drain voltage (V.sub.d) is at power supply voltage (V.sub.cc) (i.e., in general a power supply may be V.sub.cc =1.8 volts). It is desirable for the off-leakage current to be minimized such that the voltage at the source is zero (V.sub.8 =0). However, if the dopants outdiffuse into the trench, for example, dopants near the source region (e.g., dopants from region 250) diffuse into the trench, then the threshold voltage near the source region becomes less than the threshold voltage in the channel and drain regions and may allow parasitic current to flow from the source 220 to the drain 230.
One example of a prior art method for forming trench isolation structures that reduce dopant outdiffusions while allowing uniform deposition of thin gate oxides is illustrated in FIGS. 3A-K. FIG. 3A illustrates a semiconductor substrate 310 with a pad oxide layer 320 and a polish stop layer 330 deposited thereon. Polish stop layer 330 and pad oxide layer 320 are then patterned and etched (typically using well known photolithographic masking and etching techniques) to form an opening 340, as illustrated in FIG. 3B.
After polish stop layer 330 and pad oxide 320 are patterned, the substrate 320 is etched to form a trench 345, as illustrated in FIG. 3C. After trench 345 is etched, however, the sidewalls of the trench are not clean, and so a preclean step is performed to remove debris from the trench sidewalls. The trench preclean step is performed using a chemistry made up of SC1, SC2, and HF, wherein SC1 is a combination of NH.sub.4 OH, H.sub.2 O.sub.2, and H.sub.2 O. The preclean step is performed long enough that the preclean consumption chemistry will consume some of the silicon semiconductor substrate 310. The of the silicon during the preclean step rounds the sharp top corners 390 of the trench beginning the reduction of the "bird's beak" effect and the formation of rounded top corners 395, as illustrated in FIG. 3D. Because the top corners of trench 345 are rounded, they will not tend to carry high electric fields and will permit the deposition of a more uniform thin gate oxide 380 (illustrated in FIG. 3K) for the formation of a semiconductor device in the active region adjacent the trench.
Trench sidewall oxide 360 is then formed in the trench, as illustrated in FIG. 3E. Trench sidewall oxide 360 is typically grown at an approximate temperature of 1000.degree. C. to an approximate thickness of 250 .ANG.. The oxidation process occurring at 1000.degree. C. continues the reduction of the "bird's beak" and the formation of rounded top corners 395. After the trench sidewall oxide 360 is formed, trench sidewall oxide 360 is subjected to an N.sub.2 O nitridation step in a nitrogen-oxide (N.sub.2 O) gas ambient and anneal step, as illustrated in FIG. 3E. The nitridation and anneal steps form an oxy-nitride surface 365 on the first oxide layer, which reduces the stresses in the trench, and a silicon oxy-nitride interface (barrier) 366 between the semiconductor substrate and the first oxide layer, which helps to eliminate dopant outdiffusion from the active region that is adjacent to the trench 345, as illustrated in FIG. 3F.
Next, the trench is filled in with an oxide (typically using chemical vapor deposition (CVD) techniques) to form trench fill oxide 370, as illustrated in FIG. 3G. The trench fill oxide 370 is then polished (or planarized) in order to remove the excess oxide above polish stop layer 330, as illustrated in FIG. 3H. As illustrated in FIG. 3I, polish stop layer 330 is then removed (typically using conventional etch techniques). After polish stop layer 330 is removed, an etch-back step is performed (typically using chemical mechanical polishing (CMP) techniques) in order to isolate trench sidewall oxide 360 and trench fill oxide 370 within the trench, as illustrated in FIG. 3J.
When forming a transistor adjacent to the trench, a gate insulating oxide layer is grown over the substrate and over the trench, and since the top corners of the trench are rounded, the gate oxide layer 380 is grown with a uniform thickness. As illustrated in FIG. 3K, the thickness of the thin gate oxide layer 380 at rounded top corners 395 is the same thickness (i.e. uniform thickness) as the gate oxide layer that lies on the horizontal surfaces of trench 345 and substrate 310. Thus, the thin gate oxide layer 380 is not as susceptible to breakdown when subjected to high electric fields.
The above described method of using N.sub.2 O nitrided-oxide trench sidewalls when fabricating isolation structures has proven beneficial when dealing with device dimensions in the 0.25.mu.-0.35.mu. technology area. However, the demand for cheaper, faster, lower power consuming microprocessors continues to increase, with 0.18.mu. device dimensions and lower often required. To make advances in this technology, it is desirable to control the thickness of the trench sidewall oxide layer below 200 .ANG. and yet still grow such a chlorinated oxide at a high temperature. However, the thickness of such an oxide cannot currently be controlled below 200 .ANG. in the desired range of temperatures. Thus, a trench isolation structure and a method for making that structure that will reduce dopant outdiffusions, will allow uniform deposition of thin gate oxides, and will permit the use of thinner gate oxides is desired.